Pixel as a Platform for “On Silicon” Partners
Jasper Display Corporation’’s (JDC) design history stretches back to 2002. As a consequencewe maintain a pixel library that ranges many sizes and can be used to quickly create custombackplanes for new customer requirements. Our pixel’s are not only small but the flatness of our die are managed from the design all the way through fabrication resulting in some of the flattest die in the industry. JDC reduces the cost, risk and time to market for our partners by enabling them with a combination of existing silicon and an ability to quickly create custom designs to their requirements.
- Flexible Backplanes and Controllers
JDC’s backplanes are active matrix digital backplanes with digital storage, featuring high bandwidth and flexible addressing. The controllers support very flexible backplane addressing to handle a wide array of modulations allowing JDC’s solution to get the most out of any material that is interfaced to the backplanes. JDC’s pixel structure supports a relatively large amount of current while maintaining a stable voltage for either current driven or voltage driven modes of backplane operation.
JDC has successfully demonstrated that our backplanes can drive μLEDs on our standard backplanes. μLEDoS systems benefit from emissive, full solid state operation, high efficiency, and high brightness. Of course, this type of systems performance is determined greatly by our partners’ μLED characteristics but our backplanes bring out the best performance from our partners’ μLEDs.
- Cell on Silicon
Dielectrophoretic force can be used to move the neutral particles in the solution. Because of JDC’s unique digital drive circuit design, a high frequency AC electric field could be constructed between the pixel electrode on silicon backplane and the upper common electrode. By pixels of different gray scale, we could have a non-uniform electric field. Thus, the solution filled between backplane and upper plane could have the effect of dielectrophoresis. Through visual observation and special algorithm, the system will produce a frame-set of particles moving path. Each frame in the set can make particles to move a unit distance to specific direction. By the order of frames, it could manipulate the movement of multiple particles simultaneously. It could be a typical application in bio-medical field. Cells could be moved and collected on Silicon. The concept of “Cell on Silicon” is implemented.
Digital vs Analog
Reliability and Accuracy
JDC’s digital drive circuits provide extremely accurate DC balance, essential to avoid long term degradation of any liquid crystal cell. There are several microdisplay devices built using JDC’s technology, which have been operated over a 10 year period without developing image sticking or flicker.
JDC’s digital drive reduces the impact of defects inherent in all semiconductor manufacturing processes. All signals to the pixel circuits from the periphery are logic signals that enable the pixel circuit to connect one of two static voltage lines to the pixel mirror. Logic signals by nature are more tolerant of voltage variations whereas the voltage on the pixel mirror needs to be precise. This precision and accuracy come by driving fine time controlled PWM data to the pixels.
Pixel Design and Operation
Digital pixel enables smallest pixel design. JDC’s 3.74 micrometer pixel pitch on its JD4704 is an example of the smallest pixel in ultra-4K resolution in production. Digital pixel design allows much higher frequency to load one bit of complete image data (only 50 microseconds to write a whole plane) and smart pixel circuitry to perform DC balance without extra write of inverse data.
Traditional digital design techniques enable smart partitioning of the backplane circuitry vs drive control mechanism (JDC’s ASIC – OCM). Digital drives also allows proper tradeoffs in various modulation algorithms to build a more optimal system to address variety of applications (display as well as nondisplay).
By using traditional digital design circuitry approach, JDC’s microdisplay backplane can use a standard, proven, high yielding, logic process and enables fully automated closed loop calibration of display systems. JDC can use various proprietary design techniques in this standard digital semiconductor process and normal CMP process to produce the flattest possible die for best liquid crystal process yield.
In comparison, the smallest analog implementation of a 4K backplane has a pixel size of 7 micrometers. This size difference and the presence of capacitors necessary for an analog pixel circuit, are important factors leading to a substantial yield and cost advantage for the digital approach.